1. Field of the Invention
Embodiments of the invention relate generally to semiconductor devices. More particularly, embodiments of the invention relate to semiconductor devices and related packaging techniques incorporating a ferrite shielding structure.
2. Description of the Related Art
The computational and data manipulation circuitry of semiconductor devices is implemented on dies formed from small portions of a silicon wafer. In and of themselves, semiconductor dies are very small and quite fragile. In their native “cut-from-the-wafer” state, semiconductor dies—while fully functional in their circuitry—are not very useful since their fragile nature prevents practical integration within a host device and their small size precludes practical connections to their internal circuitry. Thus, the need for effective semiconductor packaging techniques arises. The terms “package” or “packaging” in this context refer to any material, process, method, or technique adapted to provide physical protection and/or electrical connection to/from a semiconductor die.
Semiconductor devices, such as microelectronic devices, memory devices, etc., typically encase their constituent semiconductor die in a package or housing in order to provide the die with protection from mechanical shock and the potentially corrosive effects of the surrounding environment. Semiconductor device packages come in a variety of form factors and types, but all functional semiconductor device packages are adapted in provide electrical connection between the semiconductor die and external circuits.
To facilitate connection with external circuits, semiconductor device packages typically provide a plurality of termination points. A “termination point” is any structure adapted to communicate an electrical signal (e.g., power, data, control, address, etc.) from a substrate, or more particularly a signal line or circuit formed on the substrate, to an external point. An “external point” is any electrically conductive structure formed outside the substrate, or more particularly a signal line or circuit formed outside (e.g., off) the substrate. Essentially any three dimensional conductive structure adapted to communicate an electrical signal from a signal line or a circuit formed on a substrate to an external point may serve as a termination point. However, common termination points include; pins, metal leads, and so-called bump structures, for example. As is well understood in the art, a “bump” may be formed in the shape of a ball or a similarly protruding structure from solder or a conductive metal/metal alloy (e.g. gold). Bumps are commonly formed as balls of conductive material formed as a connection means for a semiconductor device. As used hereafter, the term “ball structure” should not be construed as being limited to only spherically shaped conductive structures. Rather, the term ball structure encompasses “bumps” of any reasonable shape and composition.
Within the foregoing context and hereafter, the term “signal line” should be broadly construed to cover any conductive structure adapted to communicate an electrical signal. Metal traces and micro-strip lines commonly formed on and in relation to substrates using conventional layout and patterning techniques are examples of signal lines. Such elements are often formed from conductive materials such as cooper (Cu), aluminum (Al), or gold (Au), or alloys containing similar conductive materials.
Termination points of various types are used in a variety of conventional semiconductor device packaging and fabrication techniques. So-called flip-chip, bump bonding, and multilevel (or stacked) packaging techniques rely on a range of different termination point structures to connect a semiconductor die within a package.
The design issues and fabrication complexities associated with semiconductor device packaging have multiplied over the years as device densities and signal frequencies have increased. High frequency signals (e.g., clock, data, and/or control signals, etc.) have well understood electromagnetic transmission properties. As these electrical signals are increasingly communicated to/from semiconductor devices at frequencies up to and beyond one Gigahertz, various signal transmission problems arise.
For example, the increasingly narrow data switching time periods associated with higher signal frequencies are more susceptible to the adverse effects of electrical interference or noise, and the potential for electromagnetic inference (EMI) rises with the frequency of the signals being communicated to/from the semiconductor device. In one particularly noteworthy phenomenon, densely integrated signal lines and termination points allow high frequency signals to be cross-coupled onto signal lines and/or termination points communicating a power signal. A “power signal” in this context is typical a DC voltage signal, such as ground, VDD, VSS, VCC, etc., intended to power a circuit within the semiconductor device, but a power signal might comprise any relatively low frequency signal. Once coupled onto signal lines or termination points communicating a power signal, the high frequencies signals are communicated throughout the semiconductor device as noise.
This problem has been addressed by several conventional solutions. In one solution, signal lines and termination points are laid out within the semiconductor device such that the possibility for high frequency signal (noise) coupling is minimized. Unfortunately, as semiconductor device densities continue to increase such layout based solutions become increasing difficult to implement. There just isn't enough available surface area on contemporary semiconductor devices to provide adequate separation between signal lines and termination points communicating power signals and those communicating high frequency signals.
In another solution, differential signal lines are used to communicate power signals. As is well understood in the art, differential signals may be used in combination to essentially cancel out high frequency noise components apparent on a signal line communicating a power signal. Unfortunately, the use of differential signal lines doubles the number of power signal lines and associated connection pins in a semiconductor device. As pin counts are rising for many other reasons, and as available surface area in contemporary semiconductor devices comes at increasing premiums, the design costs associated with the use of differential signal lines are increasingly prohibitive.
In still another solution, electromagnetic obstacles are provided to block or eliminate high frequency noise components apparent on a signal line or connection point. Many of these electromagnetic obstacle based solutions are implemented at the package level or higher (e.g., board level) within a system integration comprising the implicated semiconductor device. For example, many System-In-Package (SIP) and Multi-Stack Package (MSP) incorporate some form of electromagnetic obstacle. The discrete decoupling capacitor is one common type of electromagnetic obstacle, but such components tend to be very large in size making their integration into highly dense semiconductor devices difficult.
Example of board level implementations of electromagnetic obstacles may be found, for example, in Japanese Patent Documents JP 1989-206688 filed Feb. 15, 1988, and JP 1991-014284 filed Jun. 13, 1989. In the first Japanese disclosure, a magnetic (ferrite) bead is provided as part of an integrated circuit spacer adapted to facilitate connection between the (outer) lead of a semiconductor package and a printed circuit board (PCB). In the second Japanese disclosure, ferrite beads are arranged around a PCB through via.
Indeed many different noise absorbing, high loss magnetic materials have previously been used in a variety of applications to reduce or eliminate high frequency noise components from an electrical path intended to communicate a signal. The cable industry has faced the problem shielding transmission lines from EMI for many years. U.S. Pat. No. 6,534,708, for example, describes a high loss magnetic material formed from a M-X-Y magnetic composition, where M is a metallic magnetic material consisting of iron (Fe), cobalt (Co), and/or nickel (Ni), X is one or more elements other than M and Y, and Y is fluorine (F), nitrogen (N), and/or oxygen (O). This material is used to clad a signal transmission cable adapted to effectively communicate a power signal in the proximity of high frequency signals.
U.S. Pat. No. 6,492,588 proposes the use of a ferrite-filed polymer and a ferrite bead within a detonation cable. The ferrite structures within the cable act as electromagnetic obstacles and tend to suppress the high frequency noise otherwise coupled onto the conducting portion of the cable.
Similarly, an actuating cable in an airbag system is shielded by the inclusion of graphite material surrounding the signal conductive portion of the cable in U.S. Pat. No. 6,686,543. The subject matter of these patents is hereby incorporated by reference.
Unfortunately, the size and application techniques associated with conventional cabling solutions and board level solution to the reduction of EMI do not suggest a solution to the problem of package level or lower EMI suppression. What is needed is a solution that does not increase signal line or pin counts in a semiconductor device, unlike the use of differential signal lines. What is needed is a solution that does not materially add to the already extreme pressures being placed on signal line and termination point layout criteria in a semiconductor device, unlike discrete electromagnetic obstacles such as decoupling capacitors. What is needed is a solution that is susceptible to implementation at a wafer level or wafer level packaging scale, unlike conventional PCB and cabling based solutions.